1. Field of the Invention
The present invention relates to semiconductor packaging, and more particularly, to 3D semiconductor packaging employing through silicon via (TSV) technology.
2. Description of the Related Art
Through silicon via (TSV) has become an increasingly popular technique in the field of 3D semiconductor packaging. In TSV, chips can be stacked on top of one another, and connected using conductive vias which are vertical pathways of interconnects that run through the chips.
Conventionally, a three-dimensional semiconductor package is formed by stacking two dice on a substrate, wherein a bottom die has a plurality of through silicon vias (TSV) which protrude from a surface of the bottom die, and another surface of the bottom die has a plurality of bumps. In the conventional method, the thinned bottom die is mounted to the package substrate directly by thermal compression bonding (TCB), and then the top die is stacked on the bottom die by the same method.
However, this conventional method encounters several serious problems. First, transportation of the thinned bottom die is a challenge. Second, during the process of stacking the bottom die, warpage of the package substrate can occur leading to problems such as a low yield rate, failure during the process of at mounting bumps, and so on. Moreover, die mounting by TCB is a relatively inefficient manufacturing process.